Creating a test bench for a design in VHDL (VHSIC Hardware Description Language) is crucial for verifying the functionality of your digital design. This article will guide you through the process of creating an effective test bench.

Introduction to VHDL Test Benches

A test bench in VHDL is a piece of code written to verify the behavior and functionality of a VHDL design, known as the Unit Under Test (UUT). The test bench generates the necessary input signals, applies them to the UUT, and monitors the outputs to ensure they match the expected results.

Steps to Create a VHDL Test Bench

1. Understand the Design Under Test (DUT): Before writing the test bench, thoroughly understand the functionality of your design. Identify the inputs, outputs, and the expected behavior of your design.

2. Create the Test Bench Skeleton: Start by creating a new VHDL file for your test bench. The test bench does not have any ports as it’s not intended to be synthesized or implemented in hardware.

   LIBRARY ieee;
   USE ieee.std_logic_1164.ALL;

   ENTITY test_bench IS
   END test_bench;

   ARCHITECTURE behavior OF test_bench IS
   -- Component declaration for the DUT
   COMPONENT moore_fsm
       PORT(
           clk : IN std_logic;
           reset : IN std_logic;
           input_signal : IN std_logic;
           output_signal : OUT std_logic
       );
   END COMPONENT;

   -- Signals to connect to DUT
   SIGNAL clk : std_logic := '0';
   SIGNAL reset : std_logic := '0';
   SIGNAL input_signal : std_logic := '0';
   SIGNAL output_signal : std_logic;

   BEGIN
   -- Instantiate the DUT
   uut: moore_fsm PORT MAP (
       clk => clk,
       reset => reset,
       input_signal => input_signal,
       output_signal => output_signal
   );

1. Generate Clock Signal: A clock signal is typically required for synchronous designs. This can be generated using a process that toggles the clock signal at regular intervals.

   -- Clock process definitions
   clk_process :process
   begin
       clk <= '0';
       wait for 10 ns;
       clk <= '1';
       wait for 10 ns;
   end process;

1. Apply Stimuli to DUT:

Write a process to generate stimuli, which includes setting initial conditions, applying test vectors, and asserting or de-asserting control signals like reset.

   stim_proc: process
   begin        
       -- Hold reset state for 20 ns.
       reset <= '1';
       wait for 20 ns;  
       reset <= '0';

       -- Apply input stimulus
       input_signal <= '1';
       wait for 20 ns;
       input_signal <= '0';
       wait for 20 ns;
       input_signal <= '1';
       wait for 40 ns;

       -- End simulation
       wait;
   end process;

1. Monitor the Outputs: Monitor the outputs by using assertions or displaying the results using text IO. This step involves checking if the output matches the expected results at various points in time.

   process(clk)
   begin
       if rising_edge(clk) then
           assert (output_signal = expected_value)
           report "Test failed" severity error;
       end if;
   end process;

1. Complete the Test Bench: Finish the architecture section and end the test bench entity.

   END behavior;

Example of a Complete Test Bench for a Moore FSM

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_bench IS
END test_bench;

ARCHITECTURE behavior OF test_bench IS

    COMPONENT moore_fsm
        PORT(
            clk : IN std_logic;
            reset : IN std_logic;
            input_signal : IN std_logic;
            output_signal : OUT std_logic
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL input_signal : std_logic := '0';
    SIGNAL output_signal : std_logic;

BEGIN

    uut: moore_fsm PORT MAP (
        clk => clk,
        reset => reset,
        input_signal => input_signal,
        output_signal => output_signal
    );

    clk_process :process
    begin
        clk <= '0';
        wait for 10 ns;
        clk <= '1';
        wait for 10 ns;
    end process;

    stim_proc: process
    begin       
        reset <= '1';
        wait for 20 ns; 
        reset <= '0';

        input_signal <= '1';
        wait for 20 ns;
        input_signal <= '0';
        wait for 20 ns;
        input_signal <= '1';
        wait for 40 ns;

        wait;
    end process;

END behavior;

Conclusion

Creating a test bench in VHDL involves understanding the DUT, creating a test bench skeleton, generating necessary signals (like the clock), applying stimuli, and monitoring outputs. This process ensures your design functions as expected before hardware implementation. Use this guide as a template and adapt it according to the specific requirements of your VHDL design.

📝 Article Author : SEMRADE Tarik
🏷️ Author position : Embedded Software Engineer
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